ASIC / RTL / Logic Design Engineer - Analytics / KPO / Research Sector (0-2 Yrs)

We are seeking a motivated and aspiring ASIC / RTL / Logic Design Engineer with 0-2 years of experience to join our dynamic team in Mumbai. This role is ideal for recent B.Tech/B.E. graduates or individuals with early-stage experience who are passionate about contributing to cutting-edge projects within the Analytics, KPO, and Research sectors. You will be involved in the design, verification, and implementation of complex digital logic circuits.

Key Responsibilities:
- Participate in the design and development of RTL (Register Transfer Level) for digital IPs and ASICs.
- Write and maintain Verilog/VHDL code for various logic modules.
- Perform functional simulation and verification of RTL designs.
- Assist in synthesis, timing analysis, and place-and-route activities.
- Collaborate with senior engineers and cross-functional teams to understand design requirements and specifications.
- Contribute to the debugging and troubleshooting of design issues.
- Document design specifications and verification results.
- Learn and apply industry-standard design methodologies and tools.