Design Verification Engineer

Role Summary: We are seeking a highly motivated and skilled Design Verification Engineer to join our dynamic team. The successful candidate will be responsible for ensuring the functional correctness and quality of our complex hardware designs through rigorous verification methodologies. You will work closely with the design team to develop and execute verification plans, create testbenches, and debug design issues.

Key Responsibilities:

• Develop and execute comprehensive verification plans and strategies for ASIC/SoC designs.
• Create and maintain verification environments using SystemVerilog, UVM, and other industry-standard methodologies.
• Write directed and constrained-random test cases to cover design specifications.
• Debug simulation failures, identify root causes, and collaborate with design engineers to resolve issues.
• Develop functional coverage models and analyze results to ensure adequate verification.
• Participate in design reviews and provide feedback from a verification perspective.
• Work with cross-functional teams, including hardware design, software, and system engineers.
• Stay up-to-date with the latest verification technologies and methodologies.