Design Verification Engineer

Role Summary: As a Design Verification Engineer at TCS, you will play a crucial role in ensuring the quality and reliability of complex hardware designs, particularly those integrated into advanced security and law enforcement systems. You will be responsible for developing and executing verification strategies, creating testbenches, and identifying design flaws to ensure that our cutting-edge solutions meet stringent performance and security requirements.

Key Responsibilities:
- Develop and implement comprehensive verification plans and methodologies for complex digital designs.
- Create and maintain verification environments using SystemVerilog, UVM, and other relevant industry standards.
- Write and execute directed and constrained-random test cases to cover design specifications.
- Debug simulation failures and work closely with design engineers to resolve issues.
- Develop and utilize formal verification techniques where applicable.
- Contribute to the development of reusable verification IP and infrastructure.
- Participate in design reviews and provide feedback from a verification perspective.
- Document verification strategies, test plans, and test results.
- Stay updated with the latest advancements in verification methodologies and tools.