Functional Verification Engineer

Role Summary:
We are seeking a highly motivated and experienced Functional Verification Engineer to join our dynamic team at Vedanta Limited. The successful candidate will be responsible for ensuring the functional correctness and quality of our complex hardware designs through rigorous verification methodologies. This role is critical in delivering robust and reliable semiconductor solutions for our advanced mining and processing technologies.

Key Responsibilities:
- Develop and execute comprehensive verification plans and testbenches for complex ASIC/SoC designs.
- Utilize SystemVerilog and UVM (Universal Verification Methodology) to create reusable verification components and environments.
- Implement directed and constrained-random verification strategies to achieve high code and functional coverage.
- Debug simulation failures, identify root causes, and work closely with design engineers to resolve issues.
- Develop and maintain verification collateral, including test cases, assertions, and coverage models.
- Participate in design reviews and provide feedback from a verification perspective.
- Stay updated with the latest verification methodologies, tools, and industry trends.
- Collaborate with cross-functional teams, including hardware design, software development, and systems engineering.