Physical Design / Layout Engineer

We are seeking a talented and motivated Physical Design / Layout Engineer to join our growing engineering team. In this role, you will be responsible for the physical implementation of complex integrated circuits (ICs) from netlist to GDSII, ensuring high performance, low power, and optimal area. You will work closely with RTL designers, verification engineers, and other cross-functional teams to achieve tape-out success.

Key Responsibilities:

Floorplanning, placement, and routing of digital IPs and full-chip designs.

Clock tree synthesis (CTS) and clock mesh implementation.

Timing closure, optimization, and sign-off (STA).

Power analysis and optimization (IR drop, EM analysis).

Physical verification (DRC, LVS, ERC).

Layout generation and optimization for analog/mixed-signal blocks.

Collaborate with RTL and verification teams to ensure design feasibility and debug issues.

Develop and maintain P&R scripts and flows.

Stay updated with the latest advancements in physical design methodologies and tools.